In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Stress can be introduced into a single crystal oriented substrate by several methods including, for example, forming a stress inducing liner on top of the substrate and around the gate region. Although stress inducing liners can be used as a means to enhance carrier mobility, further improvement is still required.
Uniaxial compressive stress can be obtained by embedding silicon germanium (SiGe) alloys in the source and drain regions of the MOSFETs, particularly pFETs. Typically, this is done by masking a polysilicon layer and performing a Si etch on the source and drain regions, followed by SiGe epitaxy. In order to ensure that the stress from the SiGe is maximized at the channel surface, a raised source/drain configuration is typically used. The raised source/drain configuration also minimizes the impact of stress relaxation in the silicided regions.
The additional Miller capacitance associated with raised source/drain regions is mitigated somewhat by the tendency of the SiGe epitaxy to form a [111] facet at the spacer edge once the vertical growth front extends beyond the original silicon surface. The term “facet” is used in the present invention to denote a change in the crystallographic orientation of the growth front during epitaxy. FIG. 1 illustrates this change in crystallographic orientation in greater detail for the case in which a SiGe epitaxy is formed providing a [100] growth plane and a [111] growth plane. This same tendency occurs on shallow trench isolation (STI) sidewalls as well, creating deep canyons which can cause significant impediments to the successful integration of embedded SiGe devices to an existing device flow. Some issues that need to be addressed in prior art embedded SiGe devices include the potential silicide shorting of the source/drain to the body in bulk semiconductors, a difficulty in contacting the device due to inadequate clearing of the middle-of-the-line (MOL) dielectric and the contact etch stop liner in the canyon (which are critical for both bulk and semiconductor-on-insulator (SOI) technologies). Further, faceted growth at the STI sidewall results in a reduction of stress in the channel, which is particularly problematic in devices with relatively small gate to STI distance.
It appears that others in the industry have avoided the deep canyon formation at the interface between the active area and the STI by recessing the STI. In doing so, the issue of contacting the device is alleviated, but the risk of silicide shorts between the source/drain and the body remain, and due to the STI pulldown, both the nFET and the pFET become vulnerable to this problem.
The problems mentioned above will now be described in reference to FIGS. 2 and 3. Specifically, FIG. 2 is a pictorial representation of a prior art pMOSFET which has been prepared using a standard CMOS fabrication process employing an n-type silicon channel region 12 located in substrate 10, which is isolated from neighboring devices by a shallow trench isolation 14 which consists of an insulating dielectric material. A gate dielectric 18 and electrode 20 are fabricated to define the device channel 12. Oxide 24 and nitride 26 sidewall spacers are employed to offset the pFET extension and source drain regions 17 from the device channel 12 in a self-aligned fashion. In order to induce stress in the channel 12, a recess etch is performed in the source and drain regions 16. The resulting cavity is then filled via epitaxial growth of a second material, suitably chosen to induce stress in the device channel 12, such as a silicon germanium alloy 28.
The silicon germanium epitaxy is intentionally formed in a raised source/drain configuration to minimize the impact of the silicide stress (tensile in the case of commonly used materials, CoSi, and NiSi) on the channel 12. The subsequent increase in Miller capacitance due to the raised source and drain is mitigated by the natural facet formation at the spacer boundary 30 during epitaxial growth. Similarly, a facet 32 is formed at the shallow trench isolation sidewall, however, because this facet extends below the gate dielectric 18, its effect is to reduce the amount of stress obtained in the device channel 12.
FIG. 3 is a pictorial representation of a prior art MOSFET structure in which the shallow trench isolation dielectric is dramatically recessed. By recessing the STI, one can avoid the formation of spacers on the STI sidewall during subsequent processing as would likely result in the case of the structure shown in FIG. 2. The existence of spacers on the STI sidewalls would result in incomplete silicidation of the source and drain and is expected to negatively impact manufacturing yield. Even if one can prevent spacer formation on the STI sidewall, another yield concern arises from the fact that the silicide 34 formed at the STI 14 edge is in close proximity to the junction edge 13, placing stringent requirements on the control needed on the STI pulldown etch, in order to avoid shorting the source or drain to the body of the device.
Another means of improving the carrier mobility is by utilizing a hybrid oriented substrate having planar surfaces of different crystal orientation. These types of substrates have recently been developed. See, for example, U.S. patent application Ser. No. 10/250,241, filed Jun. 23, 2003 and U.S. patent application Ser. No. 10/696,634, filed Oct. 29, 2003. Additionally, hybrid-orientated metal oxide semiconductor field effect transistors (MOSFETs) have recently demonstrated significantly higher circuit performance at the 90 nm technology node. Although hybrid oriented substrates having planar surfaces of different crystal orientation can increase the carrier mobility, further improvement is needed in order to keep the performance scaling as devices are being scaled.
In view of the above, there is a need for providing embedded stress-inducing devices in which deep canyon formation at the interface between the active area and the trench isolation is avoided, without requiring trench isolation pulldown, thereby eliminating the concern of the silicide source/drain to body shorts and contact issues.